/******************************************************************************
 * @Filename     : udk.h
 *
 * @Version      : V1.0
 * @Subversion   : $
 * @Last modified: 04/02/2020 9:25:01
 * @Modified by  : Mxy
 *
 * @Brief        : SKY2412 series peripheral access layer header file.
 *                 This file contains all the peripheral register's definitions,
 *                 bits definitions and memory mapping for SKY2412 series MCU.
 *
 * Copyright (C) 2020 SKYRELAY Technology co.,Ltd All rights reserved.
 *****************************************************************************/

#ifndef __RC2412_H__
#define __RC2412_H__

#ifdef __cplusplus
extern "C" {
#endif

/** @addtogroup sky2412_Definitions SKY2412 Definitions
  This file defines all structures and symbols for SKY2412:
    - interrupt numbers
    - registers and bit fields
    - peripheral base address
    - peripheral ID
    - Peripheral definitions
  @{
*/

/******************************************************************************/
/*                Processor and Core Peripherals                              */
/******************************************************************************/
/** @addtogroup sky2412_CMSIS Device CMSIS Definitions
  Configuration of the Cortex-M0 Processor and Core Peripherals
  @{
*/

/**
 * @details  Interrupt Number Definition. The maximum of 32 Specific Interrupts are possible.
 */
typedef enum IRQn {
    /******  Cortex-M0 Processor Exceptions Numbers *****************************************/

    NonMaskableInt_IRQn   = -14,           /* 2 Non Maskable Interrupt                           */
    HardFault_IRQn        = -13,           /* 3 Cortex-M0 Hard Fault Interrupt                   */
    SVCall_IRQn           = -5,            /* 11 Cortex-M0 SV Call Interrupt                     */
    PendSV_IRQn           = -2,            /* 14 Cortex-M0 Pend SV Interrupt                     */
    SysTick_IRQn          = -1,            /* 15 Cortex-M0 System Tick Interrupt                 */
    /******  SKY2412 specific Interrupt Numbers ***********************************************/
    GPIO_IRQn              = 0,      /* GPIO interrupt                                           */
    GPIO_E0_IRQn           = 1,      /* GPIO interrupt                                           */
    GPIO_E1_IRQn           = 2,      /* GPIO interrupt                                           */
    USCI0_IRQn             = 3,      /* USCI0 interrupt                                          */
    USCI1_IRQn             = 4,      /* USCI1 interrupt                                          */
    USCI2_IRQn             = 5,      /* USCI2 interrupt                                          */
    USCI3_IRQn             = 6,      /* USCI3 interrupt                                          */
    BB_IRQn                = 7,      /* BB interrupt                                             */
    WDT_IRQn               = 8,      /* Watch Dog Timer interrupt                                */
    RTC0_IRQn              = 9,      /* Real Timer Counter interrupt                             */
    QSPI0_IRQn             = 10,     /* QSPI0 interrupt                                          */
    QSPI1_IRQn             = 11,     /* QSPI1 interrupt                                          */
    TMRA_IRQn              = 12,     /* TimerA interrupt                                         */
    TMRB0_IRQn             = 13,     /* TimerB 0 interrupt                                       */
    TMRB1_IRQn             = 14,     /* TimerB 1 interrupt                                       */
    TMRB2_IRQn             = 15,     /* TimerB 2 interrupt                                       */
    TMRB3_IRQn             = 16,     /* TimerB 3 interrupt                                       */
    RTC1_IRQn              = 17,     /* Real Timer1 Counter interrupt                            */
} IRQn_Type;

/*
 * ==========================================================================
 * ----------- Processor and Core Peripheral Section ------------------------
 * ==========================================================================
 */

/* Configuration of the Cortex-M0 Processor and Core Peripherals */
#define __CM0_REV                0x0201    /* Core Revision r2p1                               */
#define __NVIC_PRIO_BITS         2         /* Number of Bits used for Priority Levels          */
#define __Vendor_SysTickConfig   0         /* Set to 1 if different SysTick Config is used     */
#define __MPU_PRESENT            0         /* MPU present or not                               */
#define __FPU_PRESENT            0         /* FPU present or not                               */

/*@}*/ /* end of group sky2412_CMSIS */
#include "sdk_core/CMSIS/Include/core_cm0.h"                      /* Cortex-M0 processor and core peripherals           */
#include "sdk_core/Device/SkyRelay/RC2412/Include/system_rc2412.h"                /* SKY2412 Series System include file                 */
#include <stdint.h>

/******************************************************************************/
/*                Device Specific Peripheral registers structures             */
/******************************************************************************/
//#if defined ( __CC_ARM  )
#pragma anon_unions
//#endif






/*--------------------- WDT ---------------------------------*/
//add by lv++
//WDT Base 0x40084000
typedef struct {
    __IO uint32_t CON;                     /*!< Offset: 0x000 ()  Register */
    __IO uint32_t STR;                     /*!< Offset: 0x004 (R/W)  WDT state Register */
    __IO uint32_t CMP;                     /*!< Offset: 0x008 (R/W)  WDT comparator low byte Register */
    __IO uint32_t CNT;                     /*!< Offset: 0x00C (R)    WDT counter 0 Register */
} WDT_T;

//WDT_CON


//WDT_STR
#define WDT_CLR_Pos                        (0)
#define WDT_CLR_Msk                        (0x1ul << WDT_CLR_Pos)
#define WDT_INTF_Pos                       (1)
#define WDT_INTF_Msk                       (0x1ul << WDT_INTF_Pos)
#define WDT_RSTF_Pos                       (2)
#define WDT_RSTF_Msk                       (0x1ul << WDT_RSTF_Pos)
#define WDT_ENF_Pos												 (3)
#define WDT_ENF_Msk                        (0x1u1 << WDT_ENF_Pos)

/*---------------------- END ---------------------------------*/

/*--------------------- RTC ---------------------------------*/
//RTC Base 0x40085000
typedef struct {
    __IO uint32_t CLR;                     /*!< Offset: 0x000 (WP)  RTC free counter clear register */
    __IO uint32_t CNT0;                    /*!< Offset: 0x004 (RO)  RTC free counter [31: 0] register */
    __IO uint32_t CNT1;                    /*!< Offset: 0x008 (RO)  RTC free counter [47:32] register */
    __IO uint32_t CMP;                  /*!< Offset: 0x00C (WR)  RTC comparator low byte  [ 7:0] register */
		__IO uint32_t PUS_CON;                 /*!< Offset: 0x010 (WR)  RTC pulse ctrl register */
	  __IO uint32_t WKU_CFG;                 /*!< Offset: 0x014 (WR)  RTC wakeup config register BIT[1]: 1,repeat 0,single BIT[0]:1,CMP*1024  0,CMP*1*/
		__IO uint32_t IRQ_CFG;                 /*!< Offset: 0x018 (WR)  RTC IRQ config BIT[1]: 1,close IRQ  0,en IRQ  BIT[0]:1,Clear IRQ */
} RTC_T;

//RTC_CLR
#define RTC_CLR_Pos                        (0)
#define RTC_CLR_Msk                        (0x1ul << RTC_CLR_Pos)

//RTC_PUS_CON
#define RTC_PH_Pos                         (0)
#define RTC_PH_Msk                         (0x3ul << RTC_PH_Pos)
#define RTC_PL_Pos                         (2)
#define RTC_PL_Msk                         (0xful << RTC_PL_Pos)
#define RTC_PINV_Pos                       (6)
#define RTC_PINV_Msk                       (0x1ul << RTC_PINV_Pos)
#define RTC_PEN_Pos                        (7)
#define RTC_PEN_Msk                        (0x1ul << RTC_PEN_Pos)

//RTC_WKU_CFG
#define RTC_STEP_Pos                       (0)
#define RTC_STEP_Msk                       (0x1ul << RTC_STEP_Pos)
#define RTC_WKU_MODE_Pos                   (1)
#define RTC_WKU_MODE_Msk                   (0x1ul << RTC_WKU_MODE_Pos)

//RTC_IRQ_CFG
#define RTC_IRQ_CLEAR_Pos                  (0)
#define RTC_IRQ_CLEAR_Msk                  (0x1ul << RTC_IRQ_CLEAR_Pos)
#define RTC_IRQ_MASK_Pos                   (1)
#define RTC_IRQ_MASK_Msk                   (0x1ul << RTC_IRQ_MASK_Pos)
#
/*---------------------- END ---------------------------------*/




/*---------------------- AON_WKU ---------------------------------*/
typedef struct {
    __IO uint32_t WKUP_MASK0;        /*!< Offset: 0x000 (R/W)  Wakup mask Register 0 */
    __IO uint32_t WKUN_MASK0;        /*!< Offset: 0x004 (R/W)  Wakup mask Register 1 */
    __IO uint32_t WKU_FLAG0 ;        /*!< Offset: 0x008 (R/W)  Wakup flag Register 0 */
} AON_WKU_T;

// WKUP_MASK0
#define AON_WKU_IO_WKUP_MASK0_Pos              (0)
#define AON_WKU_IO_WKUP_MASK0_Msk              (0x1ul << AON_WKU_IO_WKUP_MASK0_Pos)
#define AON_WKU_IO_WKUP_MASK1_Pos              (1)
#define AON_WKU_IO_WKUP_MASK1_Msk              (0x1ul << AON_WKU_IO_WKUP_MASK1_Pos)
#define AON_WKU_IO_WKUP_MASK2_Pos              (2)
#define AON_WKU_IO_WKUP_MASK2_Msk              (0x1ul << AON_WKU_IO_WKUP_MASK2_Pos)
#define AON_WKU_IO_WKUP_MASK3_Pos              (3)
#define AON_WKU_IO_WKUP_MASK3_Msk              (0x1ul << AON_WKU_IO_WKUP_MASK3_Pos)
#define AON_WKU_IO_WKUP_MASK4_Pos              (4)
#define AON_WKU_IO_WKUP_MASK4_Msk              (0x1ul << AON_WKU_IO_WKUP_MASK4_Pos)
#define AON_WKU_IO_WKUP_MASK5_Pos              (5)
#define AON_WKU_IO_WKUP_MASK5_Msk              (0x1ul << AON_WKU_IO_WKUP_MASK5_Pos)
#define AON_WKU_IO_WKUP_MASK6_Pos              (6)
#define AON_WKU_IO_WKUP_MASK6_Msk              (0x1ul << AON_WKU_IO_WKUP_MASK6_Pos)
#define AON_WKU_IO_WKUP_MASK7_Pos              (7)
#define AON_WKU_IO_WKUP_MASK7_Msk              (0x1ul << AON_WKU_IO_WKUP_MASK7_Pos)
#define AON_WKU_IO_WKUP_MASK8_Pos              (8)
#define AON_WKU_IO_WKUP_MASK8_Msk              (0x1ul << AON_WKU_IO_WKUP_MASK8_Pos)
#define AON_WKU_IO_WKUP_MASK9_Pos              (9)
#define AON_WKU_IO_WKUP_MASK9_Msk              (0x1ul << AON_WKU_IO_WKUP_MASK9_Pos)
#define AON_WKU_IO_WKUP_MASK10_Pos             (10)
#define AON_WKU_IO_WKUP_MASK10_Msk             (0x1ul << AON_WKU_IO_WKUP_MASK10_Pos)
#define AON_WKU_IO_WKUP_MASK11_Pos             (11)
#define AON_WKU_IO_WKUP_MASK11_Msk             (0x1ul << AON_WKU_IO_WKUP_MASK11_Pos)
#define AON_WKU_IO_WKUP_MASK12_Pos             (12)
#define AON_WKU_IO_WKUP_MASK12_Msk             (0x1ul << AON_WKU_IO_WKUP_MASK12_Pos)
#define AON_WKU_IO_WKUP_MASK13_Pos             (13)
#define AON_WKU_IO_WKUP_MASK13_Msk             (0x1ul << AON_WKU_IO_WKUP_MASK13_Pos)
#define AON_WKU_IO_WKUP_MASK14_Pos             (14)
#define AON_WKU_IO_WKUP_MASK14_Msk             (0x1ul << AON_WKU_IO_WKUP_MASK14_Pos)
#define AON_WKU_IO_WKUP_MASK15_Pos             (15)
#define AON_WKU_IO_WKUP_MASK15_Msk             (0x1ul << AON_WKU_IO_WKUP_MASK15_Pos)

// WKUN_MASK0
#define AON_WKU_IO_WKUN_MASK0_Pos              (0)
#define AON_WKU_IO_WKUN_MASK0_Msk              (0x1ul << AON_WKU_IO_WKUN_MASK0_Pos)
#define AON_WKU_IO_WKUN_MASK1_Pos              (1)
#define AON_WKU_IO_WKUN_MASK1_Msk              (0x1ul << AON_WKU_IO_WKUN_MASK1_Pos)
#define AON_WKU_IO_WKUN_MASK2_Pos              (2)
#define AON_WKU_IO_WKUN_MASK2_Msk              (0x1ul << AON_WKU_IO_WKUN_MASK2_Pos)
#define AON_WKU_IO_WKUN_MASK3_Pos              (3)
#define AON_WKU_IO_WKUN_MASK3_Msk              (0x1ul << AON_WKU_IO_WKUN_MASK3_Pos)
#define AON_WKU_IO_WKUN_MASK4_Pos              (4)
#define AON_WKU_IO_WKUN_MASK4_Msk              (0x1ul << AON_WKU_IO_WKUN_MASK4_Pos)
#define AON_WKU_IO_WKUN_MASK5_Pos              (5)
#define AON_WKU_IO_WKUN_MASK5_Msk              (0x1ul << AON_WKU_IO_WKUN_MASK5_Pos)
#define AON_WKU_IO_WKUN_MASK6_Pos              (6)
#define AON_WKU_IO_WKUN_MASK6_Msk              (0x1ul << AON_WKU_IO_WKUN_MASK6_Pos)
#define AON_WKU_IO_WKUN_MASK7_Pos              (7)
#define AON_WKU_IO_WKUN_MASK7_Msk              (0x1ul << AON_WKU_IO_WKUN_MASK7_Pos)
#define AON_WKU_IO_WKUN_MASK8_Pos              (8)
#define AON_WKU_IO_WKUN_MASK8_Msk              (0x1ul << AON_WKU_IO_WKUN_MASK8_Pos)
#define AON_WKU_IO_WKUN_MASK9_Pos              (9)
#define AON_WKU_IO_WKUN_MASK9_Msk              (0x1ul << AON_WKU_IO_WKUN_MASK9_Pos)
#define AON_WKU_IO_WKUN_MASK10_Pos             (10)
#define AON_WKU_IO_WKUN_MASK10_Msk             (0x1ul << AON_WKU_IO_WKUN_MASK10_Pos)
#define AON_WKU_IO_WKUN_MASK11_Pos             (11)
#define AON_WKU_IO_WKUN_MASK11_Msk             (0x1ul << AON_WKU_IO_WKUN_MASK11_Pos)
#define AON_WKU_IO_WKUN_MASK12_Pos             (12)
#define AON_WKU_IO_WKUN_MASK12_Msk             (0x1ul << AON_WKU_IO_WKUN_MASK12_Pos)
#define AON_WKU_IO_WKUN_MASK13_Pos             (13)
#define AON_WKU_IO_WKUN_MASK13_Msk             (0x1ul << AON_WKU_IO_WKUN_MASK13_Pos)
#define AON_WKU_IO_WKUN_MASK14_Pos             (14)
#define AON_WKU_IO_WKUN_MASK14_Msk             (0x1ul << AON_WKU_IO_WKUN_MASK14_Pos)
#define AON_WKU_IO_WKUN_MASK15_Pos             (15)
#define AON_WKU_IO_WKUN_MASK15_Msk             (0x1ul << AON_WKU_IO_WKUN_MASK15_Pos)

// WKU_FLAG0
#define AON_WKU_IO_WKU_FLAG0_Pos               (0)
#define AON_WKU_IO_WKU_FLAG0_Msk               (0x1ul << AON_WKU_IO_WKU_FLAG0_Pos)
#define AON_WKU_IO_WKU_FLAG1_Pos               (1)
#define AON_WKU_IO_WKU_FLAG1_Msk               (0x1ul << AON_WKU_IO_WKU_FLAG1_Pos)
#define AON_WKU_IO_WKU_FLAG2_Pos               (2)
#define AON_WKU_IO_WKU_FLAG2_Msk               (0x1ul << AON_WKU_IO_WKU_FLAG2_Pos)
#define AON_WKU_IO_WKU_FLAG3_Pos               (3)
#define AON_WKU_IO_WKU_FLAG3_Msk               (0x1ul << AON_WKU_IO_WKU_FLAG3_Pos)
#define AON_WKU_IO_WKU_FLAG4_Pos               (4)
#define AON_WKU_IO_WKU_FLAG4_Msk               (0x1ul << AON_WKU_IO_WKU_FLAG4_Pos)
#define AON_WKU_IO_WKU_FLAG5_Pos               (5)
#define AON_WKU_IO_WKU_FLAG5_Msk               (0x1ul << AON_WKU_IO_WKU_FLAG5_Pos)
#define AON_WKU_IO_WKU_FLAG6_Pos               (6)
#define AON_WKU_IO_WKU_FLAG6_Msk               (0x1ul << AON_WKU_IO_WKU_FLAG6_Pos)
#define AON_WKU_IO_WKU_FLAG7_Pos               (7)
#define AON_WKU_IO_WKU_FLAG7_Msk               (0x1ul << AON_WKU_IO_WKU_FLAG7_Pos)
#define AON_WKU_IO_WKU_FLAG8_Pos               (8)
#define AON_WKU_IO_WKU_FLAG8_Msk               (0x1ul << AON_WKU_IO_WKU_FLAG8_Pos)
#define AON_WKU_IO_WKU_FLAG9_Pos               (9)
#define AON_WKU_IO_WKU_FLAG9_Msk               (0x1ul << AON_WKU_IO_WKU_FLAG9_Pos)
#define AON_WKU_IO_WKU_FLAG10Pos               (10)
#define AON_WKU_IO_WKU_FLAG10Msk               (0x1ul << AON_WKU_IO_WKU_FLAG10Pos)
#define AON_WKU_IO_WKU_FLAG11Pos               (11)
#define AON_WKU_IO_WKU_FLAG11Msk               (0x1ul << AON_WKU_IO_WKU_FLAG11Pos)
#define AON_WKU_IO_WKU_FLAG12Pos               (12)
#define AON_WKU_IO_WKU_FLAG12Msk               (0x1ul << AON_WKU_IO_WKU_FLAG12Pos)
#define AON_WKU_IO_WKU_FLAG13Pos               (13)
#define AON_WKU_IO_WKU_FLAG13Msk               (0x1ul << AON_WKU_IO_WKU_FLAG13Pos)
#define AON_WKU_IO_WKU_FLAG14Pos               (14)
#define AON_WKU_IO_WKU_FLAG14Msk               (0x1ul << AON_WKU_IO_WKU_FLAG14Pos)
#define AON_WKU_IO_WKU_FLAG15Pos               (15)
#define AON_WKU_IO_WKU_FLAG15Msk               (0x1ul << AON_WKU_IO_WKU_FLAG15Pos)
#define AON_WKU_WDT_FLAG0_Pos                  (16)
#define AON_WKU_WDT_FLAG0_Msk                  (0x1ul << AON_WKU_WDT_FLAG0_Pos)

/*---------------------- END ---------------------------------*/




/*---------------------- SYSC ---------------------------------*/
typedef struct {
    __IO uint32_t CLK_EN;                /*!< Offset: 0x000 (R/W)  System clock eanble Register */
    __IO uint32_t SWRST;                 /*!< Offset: 0x004 (R/W)  System software reset Register */
    __IO uint32_t CLK_SEL;              /*!< Offset: 0x008 (R/W)  ANA0 Register */
    __IO uint32_t CHIP_ID;              /*!< Offset: 0x00C (R/W)  ANA1 Register */
} SYSC_T;
/*---------------------- END ---------------------------------*/

//CLK_EN
#define WDT_PATTERN_EN_Pos                    (24)   //The value 0x69 is Close WDT work clock, others is Open WDT work
#define RTC1_PATTERN_Pos                      (20)   //The value 0x3C is Close RTC work clock, others is Open RTC work
#define RTC0_PATTERN_Pos                      (16)   //The value 0x3C is Close RTC work clock, others is Open RTC work

#define LEOPARD_EN_Pos                        (13)
#define WKU_EN_Pos                            (12)
#define BBE_EN_Pos                            (11)
#define GPIO_EN_Pos                           (10)
#define QSPI1_EN_Pos                          (9)
#define QSPI0_EN_Pos                          (8)
#define PINMUX_EN_Pos                         (7)
#define CRC_EN_Pos                            (6)
#define TMRB_EN_CLK_Pos                       (5)
#define TMRA_EN_Pos                           (4)
#define USCI3_EN_Pos                          (3)
#define USCI2_EN_Pos                          (2)
#define USCI1_EN_Pos                          (1)
#define USCI0_EN_Pos                          (0)


#define WDT_PATTERN_EN_Msk                    (0xFFul << WDT_PATTERN_EN_Pos)
#define RTC1_PATTERN_SW_Msk                   (0xFul << RTC1_PATTERN_Pos)
#define RTC0_PATTERN_SW_Msk                   (0xFul << RTC0_PATTERN_Pos)

#define LEOPARD_EN_Msk                        (0x1ul << LEOPARD_EN_Pos     )
#define WKU_EN_Msk                            (0x1ul << WKU_EN_Pos         )
#define BBE_EN_Msk                            (0x1ul << BBE_EN_Pos         )
#define GPIO_EN_Msk                           (0x1ul << GPIO_EN_Pos        )
#define QSPI0_EN_Msk                          (0x1ul << QSPI0_EN_Pos       )
#define QSPI1_EN_Msk                          (0x1ul << QSPI1_EN_Pos       )
#define PINMUX_EN_Msk                         (0x1ul << PINMUX_EN_Pos      )
#define CRC_EN_Msk                            (0x1ul << CRC_EN_Pos         )
#define TMRB_EN_CLK_Msk                       (0x1ul << TMRB_EN_CLK_Pos    )
#define TMRA_EN_Msk                           (0x1ul << TMRA_EN_Pos        )
#define USCI0_EN_Msk                          (0x1ul << USCI0_EN_Pos       )
#define USCI1_EN_Msk                          (0x1ul << USCI1_EN_Pos       )
#define USCI2_EN_Msk                          (0x1ul << USCI2_EN_Pos       )
#define USCI3_EN_Msk                          (0x1ul << USCI3_EN_Pos       )

//RTC&WDT pattern
#define WDT_PATTERN_DISABLE                   0x69ul
#define RTC0_PATTERN_DISABLE                  0xFul
#define RTC1_PATTERN_DISABLE                  0xFul

//RST
#define WDT_SWRST_N_Pos                       (24)
#define RTC_SWRST_N_Pos                       (16)
#define WKU_SWRST_N_Pos                       (12)
#define BBE_SWRST_N_Pos                        (11)
#define GPIO_SWRST_N_Pos                      (10)
#define QSPI1_SWRST_N_Pos                     (9)
#define QSPI0_SWRST_N_Pos                     (8)
#define PINMUX_SWRST_N_Pos                    (7)
#define CRC_SWRST_N_Pos                       (6)
#define TMRB_SWRST_N_Pos                      (5)
#define TMRA_SWRST_N_Pos                      (4)
#define USCI3_SWRST_N_Pos                     (3)
#define  USCI2_SWRST_N_Pos                    (2)
#define  USCI1_SWRST_N_Pos                    (1)
#define USCI0_SWRST_N_Pos                     (0)

#define WDT_SWRST_N_Msk                       (0x1ul << WDT_SWRST_N_Pos   )
#define RTC_SWRST_N_Msk                       (0x1ul << RTC_SWRST_N_Pos   )
#define WKU_SWRST_N_Msk                       (0x1ul << WKU_SWRST_N_Pos   )
#define BBE_SWRST_N_Msk                        (0x1ul << BBE_SWRST_N_Pos    )
#define GPIO_SWRST_N_Msk                      (0x1ul << GPIO_SWRST_N_Pos  )
#define QSPI0_SWRST_N_Msk                     (0x1ul << QSPI0_SWRST_N_Pos )
#define QSPI1_SWRST_N_Msk                     (0x1ul << QSPI1_SWRST_N_Pos )
#define PINMUX_SWRST_N_Msk                    (0x1ul << PINMUX_SWRST_N_Pos)
#define CRC_SWRST_N_Msk                       (0x1ul << CRC_SWRST_N_Pos   )
#define TMRB_SWRST_N_Msk                      (0x1ul << TMRB_SWRST_N_Pos  )
#define TMRA_SWRST_N_Msk                      (0x1ul << TMRA_SWRST_N_Pos  )
#define USCI0_SWRST_N_Msk                     (0x1ul << USCI0_SWRST_N_Pos )
#define USCI1_SWRST_N_Msk                     (0x1ul << USCI1_SWRST_N_Pos )
#define USCI2_SWRST_N_Msk                     (0x1ul << USCI2_SWRST_N_Pos )
#define USCI3_SWRST_N_Msk                     (0x1ul << USCI3_SWRST_N_Pos )
/*CLK_SEL*/
#define BBE_ISO_SEL_MSK                       (0x1ul <<16)  //1: lock   0: unlock
#define LRC_SEL_MSK                           (0x1ul <<8)   //1: slow   0: fast
#define LRC_DIV2_MSK                          (0x1ul <<0)   // 2^N div 
#define LRC_DIV4_MSK                          (0x2ul <<0)   // 2^N div 
#define LRC_DIV8_MSK                          (0x3ul <<0)   // 2^N div 
#define LRC_DIV16_MSK                         (0x4ul <<0)   // 2^N div 
#define LRC_DIV32_MSK                         (0x5ul <<0)   // 2^N div 
#define LRC_DIV64_MSK                         (0x6ul <<0)   // 2^N div 
#define LRC_DIV128_MSK                        (0x7ul <<0)   // 2^N div 
/*---------------------- USCI ---------------------------------*/
typedef struct {
    __IO uint32_t STA;
    __IO uint32_t TRX;
    __IO uint32_t CMD;
    __IO uint32_t IMR;
    __IO uint32_t EMR;
    __IO uint32_t ISR;
    __IO uint32_t ESR;
    __IO uint32_t CFG0;
    __IO uint32_t CFG1;
    __IO uint32_t BAUD;
    __IO uint32_t MOD;
    __IO uint32_t CLK_DIV;
} USCI_T;

//STA
#define USCI_STA_TX_Pos                (0)
#define USCI_STA_TX_Msk                (0x01ul << USCI_STA_TX_Pos)
#define USCI_STA_RX_Pos                (1)
#define USCI_STA_RX_Msk                (0x01ul << USCI_STA_RX_Pos)

//IMR
#define USCI_IMR_TXE_Pos               (0)
#define USCI_IMR_TXE_Msk               (0x01ul << USCI_IMR_TXE_Pos)
#define USCI_IMR_RXNE_Pos              (1)
#define USCI_IMR_RXNE_Msk              (0x01ul << USCI_IMR_RXNE_Pos)
#define USCI_IMR_TE_Pos                (2)
#define USCI_IMR_TE_Msk                (0x01ul << USCI_IMR_TE_Pos)

//EMR
#define USCI_EMR_ROVR_Pos              (0)
#define USCI_EMR_ROVR_Msk              (0x01ul << USCI_EMR_ROVR_Pos)
#define USCI_EMR_RPAR_Pos              (1)
#define USCI_EMR_RPAR_Msk              (0x01ul << USCI_EMR_RPAR_Pos)

//ISR
#define USCI_ISR_TXE_Pos               (0)
#define USCI_ISR_TXE_Msk               (0x01ul << USCI_ISR_TXE_Pos)
#define USCI_ISR_RXNE_Pos              (1)
#define USCI_ISR_RXNE_Msk              (0x01ul << USCI_ISR_RXNE_Pos)
#define USCI_ISR_TE_Pos                (2)
#define USCI_ISR_TE_Msk                (0x01ul << USCI_ISR_TE_Pos)

//ESR
#define USCI_ISR_ROVR_Pos              (0)
#define USCI_ISR_ROVR_Msk              (0x01ul << USCI_EMR_ROVR_Pos)
#define USCI_ISR_RPAR_Pos              (1)
#define USCI_ISR_RPAR_Msk              (0x01ul << USCI_EMR_RPAR_Pos)

//CFG0
#define USCI_CFG0_WK_MODE_Pos          (0)
#define USCI_CFG0_WK_MODE_Msk          (0x03ul << USCI_CFG0_WK_MODE_Pos)
#define USCI_CFG0_TX_DMA_Pos           (4)
#define USCI_CFG0_TX_DMA_Msk           (0x01ul << USCI_CFG0_TX_DMA_Pos)
#define USCI_CFG0_RX_DMA_Pos           (5)
#define USCI_CFG0_RX_DMA_Msk           (0x01ul << USCI_CFG0_RX_DMA_Pos)

//CFG1
#define USCI_CFG1_TX_EN_Pos            (0)
#define USCI_CFG1_TX_EN_Msk            (0x01ul << USCI_CFG1_TX_EN_Pos)
#define USCI_CFG1_RX_EN_Pos            (1)
#define USCI_CFG1_RX_EN_Msk            (0x01ul << USCI_CFG1_RX_EN_Pos)
#define USCI_CFG1_HALF_DUPLEX_Pos      (2)
#define USCI_CFG1_HALF_DUPLEX_Msk      (0x01ul << USCI_CFG1_HALF_DUPLEX_Pos)
#define USCI_CFG1_DATA_LEN_Pos         (4)
#define USCI_CFG1_DATA_LEN_Msk         (0x03ul << USCI_CFG1_DATA_LEN_Pos)
#define USCI_CFG1_LSB_Pos              (6)
#define USCI_CFG1_LSB_Msk              (0x01ul << USCI_CFG1_LSB_Pos)
#define USCI_CFG1_PAR_TYP_Pos          (8)
#define USCI_CFG1_PAR_TYP_Msk          (0x01ul << USCI_CFG1_PAR_TYP_Pos)
#define USCI_CFG1_PAR_EN_Pos           (9)
#define USCI_CFG1_PAR_EN_Msk           (0x01ul << USCI_CFG1_PAR_EN_Pos)
#define USCI_CFG1_STOP_LEN_Pos         (10)
#define USCI_CFG1_STOP_LEN_Msk         (0x01ul << USCI_CFG1_STOP_LEN_Pos)
#define USCI_CFG1_BIT_INV_Pos          (12)
#define USCI_CFG1_BIT_INV_Msk          (0x01ul << USCI_CFG1_BIT_INV_Pos)
#define USCI_CFG1_TRX_NEG_Pos          (16)
#define USCI_CFG1_TRX_NEG_Msk          (0x01ul << USCI_CFG1_TRX_NEG_Pos)
#define USCI_CFG1_CLKP_Pos             (17)
#define USCI_CFG1_CLKP_Msk             (0x01ul << USCI_CFG1_CLKP_Pos)
#define USCI_CFG1_SLV_SEL_Pos          (18)
#define USCI_CFG1_SLV_SEL_Msk          (0x01ul << USCI_CFG1_SLV_SEL_Pos)
#define USCI_CFG1_CS_LVL_Pos           (19)
#define USCI_CFG1_CS_LVL_Msk           (0x01ul << USCI_CFG1_CS_LVL_Pos)
#define USCI_CFG1_CS_SEL_Pos           (20)
#define USCI_CFG1_CS_SEL_Msk           (0x1Ful << USCI_CFG1_CS_SEL_Pos)

//BAUD
#define USCI_BAUD_DIV_Pos              (0)
#define USCI_BAUD_DIV_Msk              (0xFFFFul << USCI_BAUD_DIV_Pos)

//MOD
#define USCI_BAUD_S16_Pos              (0)
#define USCI_BAUD_S16_Msk              (0x01ul << USCI_BAUD_S16_Pos)
#define USCI_BAUD_SDIV_Pos             (1)
#define USCI_BAUD_SDIV_Msk             (0x07ul << USCI_BAUD_SDIV_Pos)
#define USCI_BAUD_FDIV_Pos             (4)
#define USCI_BAUD_FDIV_Msk             (0x0Ful << USCI_BAUD_FDIV_Pos)

//CLK_DIV
#define USCI_CLK_DIV_Pos               (0)
#define USCI_CLK_DIV_Msk               (0x0Ful << USCI_CLK_DIV_Pos)

/*---------------------- END ---------------------------------*/



/*---------------------- QSPI ---------------------------------*/
//
typedef struct {
    __IO uint32_t CTRL;
    __IO uint32_t ST;
    union
    {
        __IO uint32_t DATA;
        __IO uint8_t DATA8[4];
    };
    __IO uint32_t CS;
    __IO uint32_t DMA;
} QSPI_T;

//CTRL
#define QSPI_CTRL_IE_Pos                (0)
#define QSPI_CTRL_IE_Msk                (0x01ul << QSPI_CTRL_IE_Pos)
#define QSPI_CTRL_BOOT_SEL_Pos          (1)
#define QSPI_CTRL_BOOT_SEL_Msk          (0x01ul << QSPI_CTRL_BOOT_SEL_Pos)
#define QSPI_CTRL_CPHA_Pos              (2)
#define QSPI_CTRL_CPHA_Msk              (0x01ul << QSPI_CTRL_CPHA_Pos)
#define QSPI_CTRL_CPOL_Pos              (3)
#define QSPI_CTRL_CPOL_Msk              (0x01ul << QSPI_CTRL_CPOL_Pos)
#define QSPI_CTRL_MSB_SEL_Pos           (4)
#define QSPI_CTRL_MSB_SEL_Msk           (0x01ul << QSPI_CTRL_MSB_SEL_Pos)
#define QSPI_CTRL_FRAME_MODE_Pos        (5)
#define QSPI_CTRL_FRAME_MODE_Msk        (0x07ul << QSPI_CTRL_FRAME_MODE_Pos)
#define QSPI_CTRL_CLK_DIV_Pos           (8)
#define QSPI_CTRL_CLK_DIV_Msk           (0xFFul << QSPI_CTRL_CLK_DIV_Pos)
#define QSPI_CTRL_DUMMY_LEN_Pos         (16)
#define QSPI_CTRL_DUMMY_LEN_Msk         (0x0Ful << QSPI_CTRL_DUMMY_LEN_Pos)
#define QSPI_CTRL_TSHSL_Pos             (20)
#define QSPI_CTRL_TSHSL_Msk             (0x0Ful << QSPI_CTRL_TSHSL_Pos)
#define QSPI_CTRL_READ_COMMAND_Pos      (24)
#define QSPI_CTRL_READ_COMMAND_Msk      (0xFFul << QSPI_CTRL_READ_COMMAND_Pos)

//ST
#define QSPI_ST_BUSY_Pos                (0)
#define QSPI_ST_BUSY_Msk                (0x01ul << QSPI_ST_BUSY_Pos)
#define QSPI_ST_IRQ_Pos                 (1)
#define QSPI_ST_IRQ_Msk                 (0x01ul << QSPI_ST_IRQ_Pos)
#define QSPI_ST_DMA_EN_Pos              (2)
#define QSPI_ST_DMA_EN_Msk              (0x01ul << QSPI_ST_DMA_EN_Pos)
#define QSPI_ST_DMA_TRAN_EN_Pos         (3)
#define QSPI_ST_DMA_TRAN_EN_Msk         (0x01ul << QSPI_ST_DMA_TRAN_EN_Pos)
#define QSPI_ST_DMA_TX_IRQ_Pos          (4)
#define QSPI_ST_DMA_TX_IRQ_Msk          (0x01ul << QSPI_ST_DMA_TX_IRQ_Pos)
#define QSPI_ST_DMA_RX_IRQ_Pos          (5)
#define QSPI_ST_DMA_RX_IRQ_Msk          (0x01ul << QSPI_ST_DMA_RX_IRQ_Pos)

//CS
#define QSPI_CS_CS_Pos                  (0)
#define QSPI_CS_CS_Msk                  (0x01ul << QSPI_CS_CS_Pos)
#define QSPI_CS_XIP_ON_Pos              (4)
#define QSPI_CS_XIP_ON_Msk              (0x01ul << QSPI_CS_XIP_ON_Pos)
#define QSPI_CS_DUMMY_BYTE_Pos          (8)
#define QSPI_CS_DUMMY_BYTE_Msk          (0xFFul << QSPI_CS_DUMMY_BYTE_Pos)

/*---------------------- END ---------------------------------*/


/*---------------------- GPIO ---------------------------------*/
//
typedef struct {
    __IO uint32_t PMODE;            /*!< Offset: 0x000 (R/W)  GPIO port mode Register */
    __IO uint32_t DOUT;             /*!< Offset: 0x004 (R/W)  GPIO data out Register */
    __IO uint32_t DOUTMASK;         /*!< Offset: 0x008 (R/W)  GPIO data out write mask Register */
    __IO uint32_t PIN;              /*!< Offset: 0x00c (R/W)  */
    __IO uint32_t INTEN;            /*!< Offset: 0x010 (R/W)  GPIO interrupt enable Register */
    __IO uint32_t INTTYPE;          /*!< Offset: 0x014 (R/W)  GPIO interrupt type Register */
    __IO uint32_t INTPOL;           /*!< Offset: 0x018 (R/W)  011:pos edge,001:neg edge,010:both edge, 1x0:low level, 1x1:high level */
    __IO uint32_t INTSTR;           /*!< Offset: 0x01C (R/W)  GPIO interrupt status Register */
} GPIO_T;


typedef struct {
    __IO uint32_t AE;         /*!< Offset: 0x000 (R/W)  Analog or digital select Register */
    __IO uint32_t AT;         /*!< Offset: 0x004 (R/W)  Digital test mode Register */
    __IO uint32_t UE;         /*!< Offset: 0x008 (R/W)  pullup pullup set Register */
    __IO uint32_t RE;         /*!< Offset: 0x00c (R/W)  pullup pullup set Register */
    __IO uint32_t OD;         /*!< Offset: 0x010 (R/W)  Opendrain  Register */
//    __IO uint32_t VCM;        /*!< Offset: 0x014 (R/W)  Power output Register */

} PIN_CTRL_T;


typedef struct {
    __IO uint32_t MUX0;
    __IO uint32_t MUX1;
} PINMUX_T;

/*---------------------- END ---------------------------------*/







/*---------------------- CRC ---------------------------------*/
typedef struct {
    __IO uint32_t CON     ;         /*!< Offset: 0x000 (R/W)  CRC16 configuration Register */
    __IO uint32_t INI     ;         /*!< Offset: 0x004 (R/W)  CRC16 initial value Register */
    __IO uint32_t DIN     ;         /*!< Offset: 0x008 (R/W)  CRC16 input data Register */
    __IO uint32_t DOUT    ;         /*!< Offset: 0x00C (R/W)  CRC16 result Register */
} CRC_T;

#define CRC_CON_START                        (1)

//CRC_CON
#define CRC_CON_START_Pos                    (0)
#define CRC_CON_START_Msk                    (0x1ul << CRC_CON_START_Pos)
#define CRC_CON_DOUT_INV_Pos                 (1)
#define CRC_CON_DOUT_INV_Msk                 (0x1ul << CRC_CON_DOUT_INV_Pos)

/*---------------------- END ---------------------------------*/

/*--------------------- TIMERA ---------------------------------*/
typedef struct
{
    __IO uint32_t TAR  ;           //0x00 16bits timer
    __IO uint32_t TACTL;           //0x04 Control register
    __IO uint32_t TAIE ;           //0x08 Timer_A Interrupt enable
    __IO uint32_t TAI  ;           //0x0c Timer_A Interrupt
    __IO uint32_t TACCTL0;         //0x10 Capture/Compare Control Register
    __IO uint32_t TACCTL1;         //0x14 Capture/Compare Control Register
    __IO uint32_t TACCTL2;         //0x18 Capture/Compare Control Register
    __IO uint32_t TACCTL3;         //0x1C Capture/Compare Control Register
    __IO uint32_t TACCTL4;         //0x20 Capture/Compare Control Register
    __IO uint32_t TACCTL5;         //0x24 Capture/Compare Control Register
    __IO uint32_t TACCTL6;         //0x28 Capture/Compare Control Register
    __IO uint32_t TACCR0;          //0x2C Capture/Compare Register
    __IO uint32_t TACCR1;          //0x30 Capture/Compare Register
    __IO uint32_t TACCR2;          //0x34 Capture/Compare Register
    __IO uint32_t TACCR3;          //0x38 Capture/Compare Register
    __IO uint32_t TACCR4;          //0x3C Capture/Compare Register
    __IO uint32_t TACCR5;          //0x40 Capture/Compare Register
    __IO uint32_t TACCR6;          //0x44 Capture/Compare Register
} TMRA_T;



#define TMRA_TAR_Pos                     (0)
#define TMRA_TAR_Msk                     (0x0000FFFFul)

#define TMRA_TACTL_Pos                   (0)
#define TMRA_TACTL_Msk                   (0x000003FFul)
#define TMRA_TASSEL_Pos                  (8)
#define TMRA_TASSEL_Msk                  (0x3ul << TMRA_TASSEL_Pos)
#define TMRA_ID_Pos                      (6)
#define TMRA_ID_Msk                      (0x3ul << TMRA_ID_Pos)
#define TMRA_IDEX_Pos                    (3)
#define TMRA_IDEX_Msk                    (0x7ul << TMRA_IDEX_Pos)
#define TMRA_MC_Pos                      (1)
#define TMRA_MC_Msk                      (0x3ul << TMRA_MC_Pos)
#define TMRA_TACLR_Pos                   (0)
#define TMRA_TACLR_Msk                   (0x1ul << TMRA_TACLR_Pos)

#define TMRA_TAIE_Pos                    (0)
#define TMRA_TAIE_Msk                    (0x0000FFFFul)
#define TMRA_DMA0_Pos                    (8)
#define TMRA_DMA1_Pos                    (9)
#define TMRA_DMA2_Pos                    (10)
#define TMRA_DMA3_Pos                    (11)
#define TMRA_DMA4_Pos                    (12)
#define TMRA_DMA5_Pos                    (13)
#define TMRA_DMA6_Pos                    (14)
#define TMRA_DMA7_Pos                    (15)
#define TMRA_DMA0_Msk                    (0x1ul << TMRA_DMA0_Pos)
#define TMRA_DMA1_Msk                    (0x1ul << TMRA_DMA1_Pos)
#define TMRA_DMA2_Msk                    (0x1ul << TMRA_DMA2_Pos)
#define TMRA_DMA3_Msk                    (0x1ul << TMRA_DMA3_Pos)
#define TMRA_DMA4_Msk                    (0x1ul << TMRA_DMA4_Pos)
#define TMRA_DMA5_Msk                    (0x1ul << TMRA_DMA5_Pos)
#define TMRA_DMA6_Msk                    (0x1ul << TMRA_DMA6_Pos)
#define TMRA_DMA7_Msk                    (0x1ul << TMRA_DMA7_Pos)
#define TMRA_IRQ0_Pos                    (0)
#define TMRA_IRQ1_Pos                    (1)
#define TMRA_IRQ2_Pos                    (2)
#define TMRA_IRQ3_Pos                    (3)
#define TMRA_IRQ4_Pos                    (4)
#define TMRA_IRQ5_Pos                    (5)
#define TMRA_IRQ6_Pos                    (6)
#define TMRA_IRQ7_Pos                    (7)
#define TMRA_IRQ0_Msk                    (0x1ul << TMRA_IRQ0_Pos)
#define TMRA_IRQ1_Msk                    (0x1ul << TMRA_IRQ1_Pos)
#define TMRA_IRQ2_Msk                    (0x1ul << TMRA_IRQ2_Pos)
#define TMRA_IRQ3_Msk                    (0x1ul << TMRA_IRQ3_Pos)
#define TMRA_IRQ4_Msk                    (0x1ul << TMRA_IRQ4_Pos)
#define TMRA_IRQ5_Msk                    (0x1ul << TMRA_IRQ5_Pos)
#define TMRA_IRQ6_Msk                    (0x1ul << TMRA_IRQ6_Pos)
#define TMRA_IRQ7_Msk                    (0x1ul << TMRA_IRQ7_Pos)

#define TMRA_TACCTL_Pos                  (0)
#define TMRA_TACCTL_Msk                  (0x0000F7FFul)
#define TMRA_CM_Pos                      (14)
#define TMRA_CM_Msk                      (0x3ul << TMRA_CM_Pos)
#define TMRA_CCIS_Pos                    (12)
#define TMRA_CCIS_Msk                    (0x3ul << TMRA_CCIS_Pos)
#define TMRA_SCCI_Pos                    (10)
#define TMRA_SCCI_Msk                    (0x1ul << TMRA_SCCI_Pos)
#define TMRA_CAP_Pos                     (9)
#define TMRA_CAP_Msk                     (0x1ul << TMRA_CAP_Pos)
#define TMRA_DEADE_Pos                   (8)
#define TMRA_DEADE_Msk                   (0x1ul << TMRA_DEADE_Pos)
#define TMRA_OUTMOD_Pos                  (5)
#define TMRA_OUTMOD_Msk                  (0x7ul << TMRA_OUTMOD_Pos)
#define TMRA_CCIE_Pos                    (4)
#define TMRA_CCIE_Msk                    (0x1ul << TMRA_CCIE_Pos)
#define TMRA_CCI_Pos                     (3)
#define TMRA_CCI_Msk                     (0x1ul << TMRA_CCI_Pos)
#define TMRA_OUT_Pos                     (2)
#define TMRA_OUT_Msk                     (0x1ul << TMRA_OUT_Pos)
#define TMRA_COV_Pos                     (1)
#define TMRA_COV_Msk                     (0x1ul << TMRA_COV_Pos)
#define TMRA_CCIFG_Pos                   (0)
#define TMRA_CCIFG_Msk                   (0x1ul << TMRA_CCIFG_Pos)

#define TMRA_TACCR_Pos                   (0)
#define TMRA_TACCR_Msk                   (0x0000FFFFul)


/*---------------------- END ---------------------------------*/

/*---------------------- TMRB ---------------------------------*/
typedef struct
{
    __IO uint32_t T0LC;            //0x00 value to be loaded into timer0
    __I  uint32_t T0CV;            //0x04 current value of timer0
    __IO uint32_t T0CTL;           //0x08 control register for timer0
    __I  uint32_t T0EOI;           //0x0c clear the interrupt form timer0
    __I  uint32_t T0ISR;           //0x10 contains the interrupt status for timer0
    __IO uint32_t T1LC;            //0x14 value to be loaded into timer1
    __I  uint32_t T1CV;            //0x18 current value of timer1
    __IO uint32_t T1CTL;           //0x1c control register for timer1
    __I  uint32_t T1EOI;           //0x20 clear the interrupt form timer1
    __I  uint32_t T1ISR;           //0x24 contains the interrupt status for timer1
    __IO uint32_t T2LC;            //0x28 value to be loaded into timer2
    __I  uint32_t T2CV;            //0x2c current value of timer2
    __IO uint32_t T2CTL;           //0x30 control register for timer2
    __I  uint32_t T2EOI;           //0x34 clear the interrupt form timer2
    __I  uint32_t T2ISR;           //0x38 contains the interrupt status for timer2
    __IO uint32_t T3LC;            //0x3c value to be loaded into timer3
    __I  uint32_t T3CV;            //0x40 current value of timer3
    __IO uint32_t T3CTL;           //0x44 control register for timer3
    __I  uint32_t T3EOI;           //0x48 clear the interrupt form timer3
    __I  uint32_t T3ISR;           //0x4c contains the interrupt status for timer3
} TMRB_T;

typedef struct
{
    __I uint32_t TSISR;
    __I uint32_t TSEOI;
    __I uint32_t TSRAWINT;
    __I uint32_t TSVSN;
} TMRBS_T;



#define TMRB_LC_Pos                      (0)
#define TMRB_LC_Msk                      (0xfffffffful)
#define TMRB_CV_Pos                      (0)
#define TMRB_LC_Msk                      (0xfffffffful)
#define TMRB_EN_Pos                      (0)
#define TMRB_EN_Msk                      (0x1ul << TMRB_EN_Pos)
#define TMRB_MOD_Pos                     (1)
#define TMRB_MOD_Msk                     (0x1ul << TMRB_MOD_Pos)
#define TMRB_IMK_Pos                     (2)
#define TMRB_IMK_Msk                     (0x1ul << TMRB_IMK_Pos)
#define TMRB_EOI_Pos                     (0)
#define TMRB_EOI_Msk                     (0x1ul << TMRB_EOI_Pos)
#define TMRB_ISR_Pos                     (0)
#define TMRB_ISR_Msk                     (0x1ul << TMRB_ISR_Pos)
/*---------------------- END ---------------------------------*/






/** @addtogroup sky2412_PERIPHERAL_MEM_MAP SKY2412 Peripheral Memory Map
  Memory Mapped Structure for SKY2412 Series Peripheral
  @{
 */
#define ROM_BASE                           ((uint32_t)0x00000000)          //// 0x00000000 ROM base address
#define SRAM_BASE                          ((uint32_t)0x20000000)          //// 0x20000000 SRAM base address
#define APBPERIPH_BASE                     ((uint32_t)0x40000000)          //// 0x40000000 APB base address
#define AHBPERIPH_BASE                     ((uint32_t)0x50000000)          //// 0x50000000 AHB base address

/*! memory map */
#define AON_BASE                           ((uint32_t)0x40010000)          //// 0x40080000 AON base address

#define PMU_BASE                           (AON_BASE + 0x2000)             //// 0x40082000 PMU base address
#define AON_WDT_BASE                       (APBPERIPH_BASE + 0x24000)      //// 0x40024000 WDT register base address
#define RTC0_BASE                          (APBPERIPH_BASE + 0x20000)      //// 0x40020000 RTC base address
#define RTC1_BASE                          (APBPERIPH_BASE + 0x30000)      //// 0x40020000 RTC base address

//meng++
#define SYSC_BASE                          (AHBPERIPH_BASE  + 0x00000)      //// 0x50000000 system control base address

#define GPIO_BASE                         (AHBPERIPH_BASE  + 0x10000)      //// 0x50010000 GPIO Port 0 base address
#define GPIO_PIN_DATA_BASE                 (AHBPERIPH_BASE  + 0x10400)      //// 0x50010400 GPIO Data Bit Operation base address
#define AON_PINC_BASE                      (0x4001C000)                     //// 0x4001C000 Always-on PIN_CTRL register base address
#define USCI0_BASE                         (APBPERIPH_BASE  + 0x00000)     //// 0x40000000 USCI0   register base address
#define USCI1_BASE                         (APBPERIPH_BASE  + 0x04000)     //// 0x40004000 USCI1   register base address
#define USCI2_BASE                         (APBPERIPH_BASE  + 0x08000)     //// 0x40008000 USCI2   register base address
#define USCI3_BASE                         (APBPERIPH_BASE  + 0x0C000)     //// 0x4000C000 USCI3   register base address

#define CRC_BASE                           (APBPERIPH_BASE  + 0x18000)     //// 0x40018000 CRC   register base address

#define QSPI0_BASE       								   (AHBPERIPH_BASE  + 0x20000)     //// 0x50020000 QSPI0 register base address; 
#define QSPI1_BASE       								   (AHBPERIPH_BASE  + 0x30000)     //// 0x50030000 QSPI1 register base address; 

#define TMRA_BASE                          (APBPERIPH_BASE  + 0x10000)     //// 0x40010000 TimerA  register base address
#define TMRB_BASE                          (APBPERIPH_BASE  + 0x14000)     //// 0x40014000 TimerB  register base address

////////////////////////////////////////////////////////////////////////////
#define ADC                                ((ADC_T *) ADC_BASE)                 //// 0x4002C000 Pointer to ADC register structurel
#define PMU                                ((PMU_T *) PMU_BASE)            //// 0x40082000 Pointer to PMU register structurel
#define WDT                                ((WDT_T *) AON_WDT_BASE)          //// 0x40084000 Pointer to WDT register structure
#define RTC0                                ((RTC_T *) RTC0_BASE)             //// 0x40085000 Pointer to RTC register structurel
#define RTC1                                ((RTC_T *) RTC1_BASE)             //// 0x40085000 Pointer to RTC register structurel

#define USCI0                              ((USCI_T *) USCI0_BASE)
#define USCI1                              ((USCI_T *) USCI1_BASE)
#define USCI2                              ((USCI_T *) USCI2_BASE)
#define USCI3                              ((USCI_T *) USCI3_BASE)

#define QSPI                               ((QSPI_T *) QSPI0_BASE)
#define QSPI1                              ((QSPI_T *) QSPI1_BASE)
#define CRC                                ((CRC_T *)  CRC_BASE)                    //// Pointer to CRC  register structure
#define TMRA                               ((TMRA_T *) TMRA_BASE)                     //// Pointer to TMRA  register structure
#define TMRB                               ((TMRB_T *) TMRB_BASE)                     //// Pointer to TMRB  register structure
#define TMRBS                              ((TMRBS_T *)(TMRB_BASE + 0x000A0))          //// Pointer to TMRBS register structure

#define AON_SYSC_BASE                      (AON_BASE       + 0x00000)      //// 0x40080000 Always-on system control base address
#define AON_WKU_BASE                       (APBPERIPH_BASE + 0x28000)      //// 0x40028000 Always-on Wakeup Controller base address

#define GPIO                              ((GPIO_T *) GPIO_BASE)           //// 0x50010000 Pointer to GPIO0 register structure
#define PINMUX                             ((PINMUX_T *) MUX_BASE)
#define PIN_CTRL                           ((PIN_CTRL_T *) AON_PINC_BASE)    //// 0x40090000 Pointer to AON_PIN_CTRL register structure

#define AON_WKU                            ((AON_WKU_T *)  AON_WKU_BASE )                    //// Pointer to NFC  register structure

#define SYSC                               ((SYSC_T *)  SYSC_BASE)        //// Pointer to NFC  register structure
#define MUX_BASE                           (AON_PINC_BASE  + 0x00018)     //// 0x40090018 PIN_MUX register base address




/*@}*/ /* end of group sky2412_PERIPHERAL_DECLARATION */

/*@}*/ /* end of group sky2412_Peripherals */

/** @addtogroup sky2412_IO_ROUTINE SKY2412 I/O Routines
  The Declaration of SKY2412 I/O Routines
  @{
 */

typedef volatile unsigned char  vu8;        ///< Define 8-bit unsigned volatile data type
typedef volatile unsigned short vu16;       ///< Define 16-bit unsigned volatile data type
typedef volatile unsigned int  vu32;       ///< Define 32-bit unsigned volatile data type

/**
  * @brief Get a 8-bit unsigned value from specified address
  * @param[in] addr Address to get 8-bit data from
  * @return  8-bit unsigned value stored in specified address
  */
#define Read_M8(addr)  (*((vu8  *) (addr)))

/**
  * @brief Get a 16-bit unsigned value from specified address
  * @param[in] addr Address to get 16-bit data from
  * @return  16-bit unsigned value stored in specified address
  * @note The input address must be 16-bit aligned
  */
#define Read_M16(addr) (*((vu16 *) (addr)))

/**
  * @brief Get a 32-bit unsigned value from specified address
  * @param[in] addr Address to get 32-bit data from
  * @return  32-bit unsigned value stored in specified address
  * @note The input address must be 32-bit aligned
  */
#define Read_M32(addr) (*((vu32 *) (addr)))

/**
  * @brief Write a 32-bit unsigned value to specified address
  * @param[in] addr Address to put 32-bit data to
  * @param[in] addr Data to be put 32-bit
  * @return  none
  * @note The input address must be 32-bit aligned
  */
#define Write_M32(addr, value) (*((vu32 *) (addr)) = value)
#define Write_M16(addr, value) (*((vu16 *) (addr)) = (uint16_t)value)
#define Write_M8(addr, value)  (*((vu8 *) (addr)) = (uint8_t)value)
/**
  * @brief Set a 32-bit unsigned value to specified I/O port
  * @param[in] port Port address to set 32-bit data
  * @param[in] value Value to write to I/O port
  * @return  None
  * @note The output port must be 32-bit aligned
  */
#define outpw(port,value)     *((volatile unsigned int *)(port)) = value

/**
  * @brief Get a 32-bit unsigned value from specified I/O port
  * @param[in] port Port address to get 32-bit data from
  * @return  32-bit unsigned value stored in specified I/O port
  * @note The input port must be 32-bit aligned
  */
#define inpw(port)            (*((volatile unsigned int *)(port)))

/**
  * @brief Set a 16-bit unsigned value to specified I/O port
  * @param[in] port Port address to set 16-bit data
  * @param[in] value Value to write to I/O port
  * @return  None
  * @note The output port must be 16-bit aligned
  */
#define outps(port,value)     *((volatile unsigned short *)(port)) = value

/**
  * @brief Get a 16-bit unsigned value from specified I/O port
  * @param[in] port Port address to get 16-bit data from
  * @return  16-bit unsigned value stored in specified I/O port
  * @note The input port must be 16-bit aligned
  */
#define inps(port)            (*((volatile unsigned short *)(port)))

/**
  * @brief Set a 8-bit unsigned value to specified I/O port
  * @param[in] port Port address to set 8-bit data
  * @param[in] value Value to write to I/O port
  * @return  None
  */
#define outpb(port,value)     *((volatile unsigned char *)(port)) = value

/**
  * @brief Get a 8-bit unsigned value from specified I/O port
  * @param[in] port Port address to get 8-bit data from
  * @return  8-bit unsigned value stored in specified I/O port
  */
#define inpb(port)            (*((volatile unsigned char *)(port)))

/**
  * @brief Set a 32-bit unsigned value to specified I/O port
  * @param[in] port Port address to set 32-bit data
  * @param[in] value Value to write to I/O port
  * @return  None
  * @note The output port must be 32-bit aligned
  */
#define outp32(port,value)    *((volatile unsigned int *)(port)) = value

/**
  * @brief Get a 32-bit unsigned value from specified I/O port
  * @param[in] port Port address to get 32-bit data from
  * @return  32-bit unsigned value stored in specified I/O port
  * @note The input port must be 32-bit aligned
  */
#define inp32(port)           (*((volatile unsigned int *)(port)))

/**
  * @brief Set a 16-bit unsigned value to specified I/O port
  * @param[in] port Port address to set 16-bit data
  * @param[in] value Value to write to I/O port
  * @return  None
  * @note The output port must be 16-bit aligned
  */
#define outp16(port,value)    *((volatile unsigned short *)(port)) = value

/**
  * @brief Get a 16-bit unsigned value from specified I/O port
  * @param[in] port Port address to get 16-bit data from
  * @return  16-bit unsigned value stored in specified I/O port
  * @note The input port must be 16-bit aligned
  */
#define inp16(port)           (*((volatile unsigned short *)(port)))

/**
  * @brief Set a 8-bit unsigned value to specified I/O port
  * @param[in] port Port address to set 8-bit data
  * @param[in] value Value to write to I/O port
  * @return  None
  */
#define outp8(port,value)     *((volatile unsigned char *)(port)) = value

/**
  * @brief Get a 8-bit unsigned value from specified I/O port
  * @param[in] port Port address to get 8-bit data from
  * @return  8-bit unsigned value stored in specified I/O port
  */
#define inp8(port)            (*((volatile unsigned char *)(port)))

/*@}*/ /* end of group sky2412_IO_ROUTINE */

/******************************************************************************/
/*                Legacy Constants                                            */
/******************************************************************************/
/** @addtogroup sky2412_legacy_Constants SKY2412 Legacy Constants
  SKY2412 Legacy Constants
  @{
*/

#ifndef NULL
#define NULL           (0)      ///< NULL pointer
#endif

#define TRUE           (1)      ///< Boolean true, define to use in API parameters or return value
#define FALSE          (0)      ///< Boolean false, define to use in API parameters or return value

#define ENABLE         (1)      ///< Enable, define to use in API parameters
#define DISABLE        (0)      ///< Disable, define to use in API parameters

/* Define one bit mask */
#define BIT0     (0x00000001)       ///< Bit 0 mask of an 32 bit integer
#define BIT1     (0x00000002)       ///< Bit 1 mask of an 32 bit integer
#define BIT2     (0x00000004)       ///< Bit 2 mask of an 32 bit integer
#define BIT3     (0x00000008)       ///< Bit 3 mask of an 32 bit integer
#define BIT4     (0x00000010)       ///< Bit 4 mask of an 32 bit integer
#define BIT5     (0x00000020)       ///< Bit 5 mask of an 32 bit integer
#define BIT6     (0x00000040)       ///< Bit 6 mask of an 32 bit integer
#define BIT7     (0x00000080)       ///< Bit 7 mask of an 32 bit integer
#define BIT8     (0x00000100)       ///< Bit 8 mask of an 32 bit integer
#define BIT9     (0x00000200)       ///< Bit 9 mask of an 32 bit integer
#define BIT10    (0x00000400)       ///< Bit 10 mask of an 32 bit integer
#define BIT11    (0x00000800)       ///< Bit 11 mask of an 32 bit integer
#define BIT12    (0x00001000)       ///< Bit 12 mask of an 32 bit integer
#define BIT13    (0x00002000)       ///< Bit 13 mask of an 32 bit integer
#define BIT14    (0x00004000)       ///< Bit 14 mask of an 32 bit integer
#define BIT15    (0x00008000)       ///< Bit 15 mask of an 32 bit integer
#define BIT16    (0x00010000)       ///< Bit 16 mask of an 32 bit integer
#define BIT17    (0x00020000)       ///< Bit 17 mask of an 32 bit integer
#define BIT18    (0x00040000)       ///< Bit 18 mask of an 32 bit integer
#define BIT19    (0x00080000)       ///< Bit 19 mask of an 32 bit integer
#define BIT20    (0x00100000)       ///< Bit 20 mask of an 32 bit integer
#define BIT21    (0x00200000)       ///< Bit 21 mask of an 32 bit integer
#define BIT22    (0x00400000)       ///< Bit 22 mask of an 32 bit integer
#define BIT23    (0x00800000)       ///< Bit 23 mask of an 32 bit integer
#define BIT24    (0x01000000)       ///< Bit 24 mask of an 32 bit integer
#define BIT25    (0x02000000)       ///< Bit 25 mask of an 32 bit integer
#define BIT26    (0x04000000)       ///< Bit 26 mask of an 32 bit integer
#define BIT27    (0x08000000)       ///< Bit 27 mask of an 32 bit integer
#define BIT28    (0x10000000)       ///< Bit 28 mask of an 32 bit integer
#define BIT29    (0x20000000)       ///< Bit 29 mask of an 32 bit integer
#define BIT30    (0x40000000)       ///< Bit 30 mask of an 32 bit integer
#define BIT31    (0x80000000)       ///< Bit 31 mask of an 32 bit integer

/* Byte Mask Definitions */
#define BYTEMsk                (0x000000FF)         ///< Mask to get bit0~bit7 from a 32 bit integer
#define BYTE1_Msk              (0x0000FF00)         ///< Mask to get bit8~bit15 from a 32 bit integer
#define BYTE2_Msk              (0x00FF0000)         ///< Mask to get bit16~bit23 from a 32 bit integer
#define BYTE3_Msk              (0xFF000000)         ///< Mask to get bit24~bit31 from a 32 bit integer

#define GET_BYTE0(u32Param)    ((u32Param & BYTEMsk)      )  /*!< Extract Byte 0 (Bit  0~ 7) from parameter u32Param */
#define GET_BYTE1(u32Param)    ((u32Param & BYTE1_Msk) >>  8)  /*!< Extract Byte 1 (Bit  8~15) from parameter u32Param */
#define GET_BYTE2(u32Param)    ((u32Param & BYTE2_Msk) >> 16)  /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */
#define GET_BYTE3(u32Param)    ((u32Param & BYTE3_Msk) >> 24)  /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */

#define OK                     0x0
#define NOK                    0x1


#define CUART_ERR_INVALID_PARA  0x55
#define ERR_INVALID_PARA (CUART_ERR_INVALID_PARA)
/*@}*/ /* end of group sky2412_legacy_Constants */

/*@}*/ /* end of group sky2412_Definitions */

#ifdef __cplusplus
}
#endif

/******************************************************************************/
/*                         Peripheral header files                            */
/******************************************************************************/
//#include "system_udk.h"

//#include "wdt.h"
//#include "pmu.h"

//#include "gpio.h"
//#include "pinmux.h"
//#include "usci.h"

////#include "rtc.h"


//#include "qspi.h"
//#include "timerA.h"		//2022.1.17 
////#include "timerB.h"
//#include "delay.h"
//#include "retarget.h"




#endif  // __SKY2412_H__
